IBM has great enthusiasm for its new Power7+ processor
The Hot Chips 24 annual conference is scheduled for next week, and companies such as IBM, Oracle, Advanced Micro Devices, Fujitsu and Intel are expected to talk chip technology.
The conference is hosted by Stanford University, and one of the most enthusiastic firms appears to be IBM for its new Power7+ processor that it will talk about, alongside its next-generation zNext CPUs for its System z mainframes.
From a die shot of the Power4 through Power7+ families of processors that IBM has shown to customers and partners, we were able to discover that the Power7+ chip had eight cores, just like the Power7 chip the precedes it.
It wasn’t clear how much embedded DRAM L3 cache memory was on that chip from looking at the die, but it was clearly more. Thanks to a performance document published on IBM’s Developer Works site, we already know that Big Blue is boosting the L3 cache size from 4 MB for each local core segment on the Power7 chip (for a total of 32 MB) to 10 MB per core on the Power7+ chip, for a total of 80 MB.
This is a tremendous amount of cache memory and is four times what Intel has put on its latest “Sandy Bridge” Xeon E5 server processors.
All that extra cache memory, which should have a dramatic effect on performance, is enabled because of the shrink from the 45 nanometer processes used to etch the Power7 chips to the 32 nanometer processes used for the Power7+ chips.
But there are some other changes to the chip in addition to making the cores smaller (the cores are basically the same) and wrapping more cache around them.
IBM’s roadmaps have been talking about accelerators, and if you poke around patches to the Linux kernel, you can see what some of them are.
We can already see that the Power7+ will have an in-nest cryptographic accelerator that supports the Advanced Encryption Standard (AES) encryption algorithm as well as the Secure Hash Algorithm-2 (SHA-2) functions developed by the National Security Agency in the U.S.
Intel’s Xeon 5600, E5, and E7 processors support AES encryption and decryption as well, and Oracle’s Sparc T4 supports both AES encryption and SHA-1 and SHA-2 hashing functions.
There could be a random number generator etched onto the Power7+ processor. RNGs are also an important part of many applications, particularly in financial services or physics simulations that require randomness.
IBM’s people were talking to the Wall Street Journal about the upcoming Hot Chips conference, and Satya Sharma let slip that the clock speeds on Power7+ chips would be 10 to 20 percent higher than those on the Power7.
Sharma is an IBM Fellow and CTO of the Power Systems line who leads the development of the Power7 and Power7+ processors.
Power 7 clock speeds range from a low of 3 GHz – on a four-core chip used in the Power 720 entry server – to a high of 3.92 GHz in the Power 780 with all eight cores turned on, and a high of 4.14 GHz in that chip running in turbo boost mode with half the cores turned off.
You’d also get 4 GHz in an eight-core chip used in the Power 795 and 4.25 GHz in a four-core variant also used in that big server.
That puts the possible range of clock speeds for Power7+ chips between 3.3 GHz and 5.1 GHz, but there could be some variations since IBM might get more clock cycles on the smaller chips and less on the larger ones.